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ASIC Synthesis and Timing Engineer
Skills
Computer EngineeringApplication-Specific Integrated CircuitsDFTLaunch VehiclesPhysical DesignPower Purchase AgreementsSatellite S
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- B.S. or M.S. in Electrical Engineering Computer Engineering or related field
- 2+ years of ASIC design experience for high-performance SoC blocks
- Proven end-to-end RTL-to-GDSII expertise using Synopsys Cadence or Siemens tools
- Strong hands-on experience with synthesis and constraints development
- Deep understanding of physical design constraints for multi-clock multi-voltage and hierarchical SoCs
- Experience with advanced FinFET process nodes
- Prior experience in convergence with offshore or outsourced PD teams or vendors
- Able to resolve formal verification issues and analyze and fix VCLP issues regarding UPF
- Experience with logic equivalence check debug and Functional ECO development and implementation with minimal database disruption
- Experience with Low power checker to validate UPF
- Familiarity with DFT integration and STA sign-off with functional ECO implementation
- Excellent communication leadership and cross-functional collaboration skills
Nice to have
- Cross-functional collaboration
- Leadership
- Hands-on problem solving
- Vendor coordination
- Fast-paced mindset
Day to day
- Implement complex SoCs for next-generation satellite and space systems from RTL handoff through synthesis and timing closure.
- Develop timing constraints and validate them across multiple voltage and process corners using foundry-qualified sign-off tools.
- Collaborate closely with architecture RTL design DFT physical design and external partners to optimize PPA integrate floorplan information and support chip bring-up.