Design Verification Engineer
Skills
ProtocolsDebuggingEnterprise Risk ManagementEthernetInternet ProtocolNetworkingSemiconductor Engineering
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- 10+ years' experience in digital IC/VLSI verification
- Proven delivery of at least two complete verification cycles from planning through sign-off
- Strong understanding of modern VLSI verification methodologies and flows
- Excellent SystemVerilog and UVM experience
- Experience building reusable coverage-driven verification environments
- Strong debugging and problem-solving skills within complex RTL designs
Nice to have
- Collaborative
- Mentoring
- Detail-oriented
- Analytical
Day to day
- Own end-to-end verification of complex digital IP and subsystem blocks
- Define verification strategies plans and functional coverage goals
- Develop scalable verification environments using SystemVerilog and UVM
- Execute block subsystem and system-level verification activities
- Debug complex RTL designs with design and architecture teams
- Drive coverage closure and ensure verification sign-off
- Mentor junior engineers and share verification best practices