RRemoteville
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Design Verification Engineer

Skills
Computer EngineeringElectronic EngineeringFormal VerificationPeer ReviewsSpecmanStatic Timing AnalysisSystemverilog
Role

What the job involves

The main requirements, responsibilities and hiring steps.

Requirements

  • Possess a BSc/MSc in Electronic Engineering Computer Engineering or Computer Science.
  • Have at least 7 years of project-proven verification experience using SystemVerilog/UVM.
  • Demonstrate expertise in creating coverage-driven self-checking verification environments and managing verification planning and implementation.

Nice to have

  • Specman/e
  • C/C++ development
  • Formal Verification
  • Technical team leadership
  • Embedded programming
  • Python/Perl scripting

Day to day

  • Work with clients on a variety of verification projects.
  • Gain exposure to different designs such as Audio Automotive Comms Processors Space and Video.
  • Travel and engage with industry conferences winning awards and shaping standards.