Remote Engineer/Senior Engineer - VLSI (RTL Synthesis and Timing Constraints) Job in UK HCLTech

Who you are

• 5+ years of hands-on experience in RTL synthesis, equivalence checking.
• Good understanding of structural Verilog, library/cells in synthesis output.
• Constraints development and management of multi partition design, top level constraints.
• Understanding of timing budgeting, able to work with RTL team.
• Experience in analysis of timing paths, identifying key issues in logic and partitioning at synthesis stage.
• Experience in debugging non-equivalent, abort points in FEV runs.
• Automation skills in scripting languages like TCL/PERL/Python/SHELL

Desirables

• Adaptability
• Innovative thinking
• Strong understanding of Verilog
• Multitasking ability
• Strong scripting skills

What the job involves

• Develop synthesis/timing constraints for subsystems and for chip top, setup synthesis flow, run synthesis on the design, fix issues and optimize constraints.
• Collaborate with Front End RTL team to refine constraints and analyze timing paths to identify key issues.
• Ensure good quality synthesis results through effective constraints and inputs optimization.