Remote Hardware Design Engineer Job in Mountain View, WY Microsoft

Who you are

• A minimum of 5 years experience in high performance analog layout in advanced FINFET CMOS process, preferably 3nm.
• Detailed knowledge of EDA tools like Cadence, Mentor, and Synopsys.
• Proficient in layout of high-performance analog blocks such as VCOs, charge pump, interpolators, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references, etc.
• Experienced with analog design and layout guidelines, and high-speed IO.

What the job involves

• Using Cadence Virtuoso design tool and flow.
• Working on highly analog IPs like analog PLL, DLL, ADC, RX, TX, OTAs, LDO, Bandgap, and Bias.
• Layout Design review presentations and layout floor-planning supervision.
• Conducting Physical LVS, DRC, DFM.