Remote Hardware Design Engineer Job in Mountain View, WY Microsoft

Who you are

• 5 plus years of experience in high performance analog layout in advanced FINFET CMOS process
• Detailed knowledge of EDA tools for Cadence, Mentor and Synopsys
• Experience with layout of high-performance analog blocks such as VCOs, chargepump, interpolators, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references
• Knowledge of analog design and layout guidelines and high-speed IO
• Experience with floor planning, block level routing and large macro level assembly

Desirables

• Experience with VCOs, chargepump, interpolators, bandgap, OTAs, PLLs, ADCs, LDOs, RX, TX, references
• Knowledge of EDA tools for Cadence, Mentor, Synopsys
• Analog design and layout guidelines
• High-speed IO experience
• Floor planning
• Block level routing
• Large macro level assembly

What the job involves

• We are looking for analog custom layout designer to contribute to the development of the high speed data interface, serial and parallel I/O, and clock generation / distribution for custom ICs
• The candidate must have a proven record of laying out high performance analog circuits in state of the art CMOS FINFET process technologies (5nm, 3nm, and beyond) and has successfully placed products into volume production
• The primary responsibility of this position entails executing IC layout of cutting edge, high-performance, high-speed, low power CMOS Interface D2D and SERDES integrated circuits in foundry CMOS process nodes in 2nm and 3nm following industry best practices