Lead Digital ASIC Design Engineer
Skills
Application-Specific Integrated CircuitsCareer DevelopmentDigital DesignsInterfacesLaunch VehiclesRadio FrequencySignal
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- B.S. or M.S. in Electrical Engineering Computer Engineering or related field
- 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks or subsystems
- 3+ years leading ASIC design teams or projects with mentoring and deliverable management
- Strong RTL design skills in SystemVerilog or Verilog with synthesis and linting experience
- Experience defining and implementing microarchitecture from architectural guidelines and analysis
- Hands-on experience with timing closure and collaboration with synthesis and static timing analysis teams
- Familiarity with DFT concepts and tools for scan and BIST insertion
- Solid understanding of SoC design flows including clock and power domain crossing timing constraints and verification methodologies
- Experience with DSP blocks for wireless communication systems such as OFDM MIMO channel estimation or DFE
- Proficiency with industry standard EDA tools for design synthesis static timing analysis and power analysis
- Strong debugging problem solving and communication skills in cross-functional teams
Nice to have
- Technical mentorship
- Cross-functional collaboration
- Startup experience
- Geographically distributed teams
Day to day
- Lead and mentor a team of digital ASIC design engineers while managing schedules deliverables and technical execution
- Design and implement microarchitecture and RTL for complex digital subsystems in advanced wireless SoCs including DSP logic interfaces and control blocks
- Collaborate with system architects analog mixed-signal teams verification and backend engineers to optimize PPA close timing and support chip bring-up production and spaceflight operations