Silicon DD Engineer
Skills
Application-Specific Integrated CircuitsDigital DesignsField-Programmable Gate ArraysGlobal Distribution SystemsLow-Power DesignRTL CodingRTL Design
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- 4+ years of experience as a Digital Design Engineer
- Recent experience with IP RTL coding within the past 2-3 years, specifically for ASIC
- Experience having worked on a design from scratch – code from the ground up
- Experience in RTL coding and coding for low power in ASICs
- Experience in digital design µArchitecture
- Strong experience with Verilog and SystemVerilog coding
- Perl, Tcl and Python (or similar) scripting experience
Nice to have
- MSEE/CS or equivalent experience
- Work on projects coded from ground up and successfully taped out
- Former Meta experience
- Developing IP for GPU, CPU, Compression, or Video ASICs
Day to day
- Collaborating on uarchitecture development and performing RTL coding on the next version of our IP
- Working on block design implementation for an IP going into future AR products
- Ensuring RTL implementation for IP blocks meets quality checks such as Lint/CDC/RDC
- Developing test plans and reviewing test coverage with the verification team
- Supervising the RTL-to-GDS flow and assisting with synthesis and timing closure
Hiring process
- 2 Rounds, 45 mins – 1 hour Coding exercises - fixed/floating point datapath design and ctrl path/FSM design in system Verilog