RemotevilleRemote VLSI Engineer - RTL Synthesis and Timing Constraints Job in UK HCLTech
VLSI Engineer - RTL Synthesis and Timing Constraints HCLTech
£ -
Constraint ProgrammingRTL VerificationRTLSSystem On A ChipUnified Power FormatVerilogVery-Large-Scale Integration
Senior (5-8 years) - Expert (9+ years)
UK
We bring together the best of technology and our people to supercharge progress.
254700+ employees
Enterprise
Role
Who you are
- Minimum 5 years of experience in RTL synthesis and equivalence checking.
- Strong proficiency in structural Verilog and expertise in library/cell selection for synthesis output.
- Skilled in multi-partition design and top-level constraint management.
- Ability to analyze timing paths and work with the Front End RTL team to refine constraints.
- Proficiency in scripting languages such as TCL, PERL, Python, or SHELL.
What the job involves
- Develop synthesis/timing constraints for subsystems and chip tops.
- Setup and manage synthesis flow.
- Run synthesis on the design, identify issues, and optimize constraints to ensure high-quality synthesis outcomes.
Application process
- Submit resume
- Technical interview
- HR interview
- Hiring decision
Company
Company mission
HCLTech is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. Our technology products and services are built on four decades of innovation, with a world-renowned management philosophy, a strong culture of invention and risk-taking, and a relentless focus on customer relationships.Company benefits
- Remote working
- Diverse and inclusive work environment
- Access to a global network of R&D facilities
- Personal and professional growth opportunities
Company values
- Innovation
- Diversity
- Social Responsibility
- Education