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Saransh Inc

 Own block- and chip-level physical implementation including floorplanning placement clock tree synthesis routing and ECO closure through sign-off.  Close timing power and area targets for high-performance compute subsystems such as systolic arrays compute tiles memory macros NoC and I/O interfaces.  Collaborate with RTL verification DFT and architecture teams while supporting tape-out milestones post-silicon debug and customer-facing technical discussions. 

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About Saransh Inc

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