Senior ASIC Physical Design Engineer
Skills
AcceleratorApplication-Specific Integrated CircuitsForm W-2Foundry ManagementHardware Bring-UpInfraredPerl
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- BSc MSc in Electronics Radio Engineering Computer Engineering or related field
- Solid grounding in digital electronics logic design and ASIC FPGA SoC fundamentals
- Experience taking a design through the full lifecycle on real hardware FPGA SoC or ASIC
- Experience with physical implementation flows and sign-off timing power and physical verification
- Proficiency with scripting in Tcl Perl or Python
- Familiarity with industry tools such as Innovus ICC2 PrimeTime StarRC Calibre RedHawk or Voltus
- Ability to work on advanced-node tape-out programs and manage foundry handoff
Nice to have
- Customer-facing
- Strong problem-solving
- Schedule pressure
Day to day
- Own block- and chip-level physical implementation including floorplanning placement clock tree synthesis routing and ECO closure through sign-off
- Close timing power and area targets for high-performance compute subsystems such as systolic arrays compute tiles memory macros NoC and I/O interfaces
- Collaborate with RTL verification DFT and architecture teams while supporting tape-out milestones post-silicon debug and customer-facing technical discussions