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Digital Design Engineer – RTL/ASIC
Skills
RTL DesignSystemVerilogVerilogCDCSynthesisStatic Timing AnalysisDFT
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- Master’s or PhD in Electrical Engineering Computer Engineering or related field
- 5+ years of RTL design experience with 2+ years in industry
- Strong digital design background including FSMs and CDC
- Proficiency in SystemVerilog
- Experience with front-end EDA tools including simulators linters and CDC checkers
- Knowledge of synthesis static timing analysis DFT and ECO flows
- Skilled in Perl or Python scripting for automation
- Proven ability to troubleshoot and optimize designs using simulation tools and waveform viewers
- Basic knowledge of memory compilers deep learning algorithms and neural networks
- Experience with PCIe interface integration and simulation
- Knowledge of SoC bus interconnect protocols such as AXI4 AXI streaming and AHB
Nice to have
- Detail-oriented
- Collaborative
- Analytical
- Problem-solving
- Innovative
Day to day
- Design and implement complex digital RTL components for AI accelerators and SoC integration.
- Define micro-architectures from product specifications and deliver clean synthesizable SystemVerilog and Verilog code.
- Collaborate with verification physical design system architecture and software teams to achieve strong performance power and area targets.
- Integrate PCIe and other IP blocks perform front-end checks and support debug timing closure and ECO activities.