RRemoteville
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Mid Level ASIC Design Engineer

Skills
Front-End DevelopmentApplication-Specific Integrated CircuitsCache CoherencyGPIOMechanical EngineeringSilicon ValidationSystemverilog
Role

What the job involves

The main requirements, responsibilities and hiring steps.

Requirements

  • 3+ years of ASIC design experience
  • Proven RTL logic design experience in multi-million gate ASICs
  • Proficiency in Verilog or SystemVerilog
  • Experience integrating CPU IP into SoC
  • Knowledge of ARM RISC-V or MIPS architectures
  • Understanding of memory hierarchy cache coherency virtual memory and multicore CPU operation
  • Familiarity with AMBA APB and AXI protocols
  • Experience with SPI eMMC MII GPIO and I2C interfaces
  • Hands-on experience across ASIC development process with front-end tools and methodologies
  • Familiarity with low power design and UPF power intent flows
  • Experience with timing closure at high frequencies is a plus
  • B.S. degree in Electrical or Computer Engineering M.S. preferred

Nice to have

  • Self-starter
  • Highly motivated
  • Dynamic startup mindset
  • Interest in AI architectures
  • Collaborative

Day to day

  • Design and implement complex RTL for multi-million gate ASICs using Verilog or SystemVerilog.
  • Author and review micro-architecture specifications and test plans while collaborating across ASIC software product and operations teams.
  • Integrate CPU and related IP into the SoC subsystem and help resolve timing power and implementation issues with physical design.
  • Perform diagnostic post-silicon validation and support lab bring-up software debugging and certification activities.