Physical Design Engineer, PnR
Skills
Analog SemiconductorsDesign Rule CheckingHTMLLayout Versus SchematicPhysical DesignSemiconductor EngineeringSignal
What the job involves
The main requirements, responsibilities and hiring steps.
Requirements
- Experience with synthesis and place-and-route flows using Synopsys Design Compiler Fusion Compiler and IC Compiler II
- Ability to own a block or subsystem within a small cross-functional physical design team
- Experience supporting tapeout milestones with clear communication and accountability
- Knowledge of UPF and multi-voltage power domains
- Experience integrating SoC interface IP such as I3C or UART
- Understanding of signoff tasks including DRC LVS EM IR and LEC/Formality
- Experience with multi-clock and CDC-aware implementation
- Experience integrating PLL or DLL macros
- Experience with DFT-aware physical implementation including OCC and MBIST
Nice to have
- Collaborative
- Curious
- Accountable
- Self-directed
- Detail-oriented
Day to day
- Implement high-performance partitions for an industry-leading AI SoC from synthesis through tapeout.
- Own block-level physical design execution, including place-and-route, timing closure, and signoff coordination.
- Collaborate closely with architects RTL designers and DFT engineers to resolve implementation and verification issues.