Principal Digital ASIC Design Engineer

Skills
Analytical SkillsApplication-Specific Integrated CircuitsArchitectureLaunch VehiclesRadio FrequencySignalSystem On A Chip
Role

What the job involves

The main requirements, responsibilities and hiring steps.

Requirements

  • B.S. or M.S. in Electrical Engineering Computer Engineering or related field
  • 10+ years of relevant digital ASIC design experience with ownership of complex subsystems
  • Proficiency in RTL design with SystemVerilog or Verilog synthesis and linting tools
  • Experience in microarchitecture definition from architecture guidance and model analysis
  • Experience closing full-chip and subsystem timing with synthesis and static analysis teams
  • Experience with DFT tools for scan and BIST insertion
  • Solid understanding of SoC design flows including clock and power domain crossing timing constraints and formal verification
  • Experience developing and integrating DSP blocks for wireless communication
  • Strong experience with EDA tools for design synthesis static timing analysis and power analysis
  • Strong debugging problem-solving and communication skills

Nice to have

  • Technical leadership
  • Mentoring ability
  • Cross-functional collaboration
  • Fast-paced mindset
  • Space startup experience
  • Distributed team experience

Day to day

  • Lead architecture, microarchitecture, RTL implementation, and integration of complex digital blocks for wireless SoCs
  • Translate high-level DSP algorithms into efficient hardware solutions and develop end-to-end DSP subsystems such as filters, beamformers, and FFT/IFFT engines
  • Collaborate across analog, mixed-signal, verification, and backend teams to optimize PPA, close timing, validate designs, and support chip bring-up through spaceflight

Hiring process

  • Apply with your application materials
  • Reasonable accommodation available upon request
  • Must meet export control eligibility requirements