Senior Application Engineer - FPGA

Skills
C++UnixSystemVerilogPythonTclPerlRTL
Role

What the job involves

The main requirements, responsibilities and hiring steps.

Requirements

  • Bachelor's degree in Electronic Engineering Computer Engineering or related technical field
  • 3-5 years of experience in ASIC or SoC design and verification
  • Proficient in SystemVerilog
  • Comfortable with C or C++ for testbench development
  • Experience working in Unix/Linux environments
  • Scripting skills in Python Tcl or Perl
  • Solid debugging skills across RTL and software layers
  • Good communication skills in English
  • Ability to explain technical issues clearly to customers and internal teams
  • Experience with hardware emulators or prototyping platforms is a strong plus
  • Knowledge of SoC protocols such as Ethernet PCIe AMBA UART or DDR is helpful

Nice to have

  • Methodical
  • Customer-focused
  • Collaborative
  • Calm under pressure
  • Self-managing
  • Detail-oriented

Day to day

  • Support customer deployments of Synopsys emulation and prototyping platforms by compiling RTL bringing up testbenches and debugging SoC-level verification issues
  • Build and troubleshoot emulation testbenches including protocol transactors C++ code memory models and automation scripts for hardware-assisted verification workflows
  • Reproduce customer-reported issues isolate root causes and collaborate with senior engineers or R&D to drive timely technical resolution