Remote FPGA Design/Verification Engineer Job in United States Pacer Staffing LLC

Who you are

• Experience with UVM verification methodology
• Experience developing test cases based off given requirements
• Experience building test benches for FPGA / ASIC designs to provide randomized stimulus
• Experience identifying and implementing necessary test exclusions
• Experience generating coverage reports code and functional
• Firsthand experience with UVM and closing functional and code coverage is required

What the job involves

• Work with low Swap radiation hardened space rated devices
• Devise a unique verification plan for a given design
• Use System Verilog and Universal Verification Methodology UVM to verify a design in a Linux-based high-performance computing environment
• Develop requirements test cases build test benches generate reports and document verification results
• Work with an independent design team to document and resolve bugs found in the design
• Support all aspects of ASIC and FPGA development including architecture design and analysis
• Support technical reviews and be able to present to internal and external stakeholders